We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

A systematic methodology to employ error-tolerance for yield improvement

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Tong-Yu Hsieh ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan ; Kuen-Jong Lee ; Chia-Lin Lu ; Breuer, M.A.

Error-tolerance is an innovative concept that can significantly improve the yield of integrated circuits (IC's) by identifying defective yet acceptable chips. A systematic method to employ this concept, however, has not been addressed. In this paper, we propose a general methodology to systematically utilize error- tolerance for practical applications. The proposed methodology explores the error-tolerance features of target designs, evaluates the acceptability of defective chips, and predicts the yield improvement that can be achieved. To illustrate and validate the proposed methodology, we employ a discrete cosine transform (DCT) circuit that has been widely used in multimedia compression systems in a case study. By applying the proposed methodology to the DCT, an error-tolerant design flow is established. Proper attributes are determined for acceptability evaluation, and corresponding test methods are developed to identify acceptable chips. Experimental results show that one can easily specify various acceptability thresholds of the identified error-tolerable attributes to obtain different degrees of yield improvement, which validates the efficiency and effectiveness of the proposed methodology.

Published in:

VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on

Date of Conference:

23-25 April 2008