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A comparison of three designs of high-frequency broadband frequency dividers is presented. The designs are optimized for high operating frequencies. Two recently published dynamic-loading frequency divider designs are optimized for their highest attainable speed. The third proposed frequency divider features a modified dynamic-loading master-slave D-latches with on-chip spiral inductors at its differential clock inputs. The proposed frequency divider is designed in TSMC 0.13-mum CMOS process and can operate in the 19-43 GHz range and dissipates 5 mW from a supply voltage of 1.5 V.
Radio Science Conference, 2008. NRSC 2008. National
Date of Conference: 18-20 March 2008