A semi-custom memory design for an asynchronous 8051 microcontroller

In this paper, we propose a methodology for interfacing synchronous IP memory blocks (read-only memory (ROM) and random-access memory (RAM)) with asynchronous-logic digital systems based on dual-rail, 4-phase signaling. The memory blocks (ROM and RAM) of an instruction-set compatible 8051 microcontroller (A8051) is implemented with Artisan IP memory blocks for the IBM 0.13 mum CMOS technology. Interface circuits play the role of (1) synchronizing all the asynchronous input channels driving the IP memory blocks, (2) single rail signaling logic to dual-rail 4-phase signaling logic conversion and vice versa, and (3) capturing synchronous signals in memory read cycles and driving asynchronous channels. The A8051 with the proposed ROM and RAM design operates at 28% higher MIPS rate (millions of instructions per second), dissipates 20% lower energy per instruction, -50% lower Et² and occupies 19% lesser area, as compared to the A8051 with register-based memory.