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A low-power monolithically stacked 3D-TCAM

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3 Author(s)
Mingjie Lin ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA ; Jianying Luo ; Yaling Ma

This paper presents three techniques to reduce the power consumption in ternary content-addressable memories (TCAMs). The first technique is to use newly developed monolithically stacked 3D-IC technology for the implementation, because vertical stacking can drastically reduce interconnect length in both matchlines and searchlines, hence reducing signal path delay and power consumption. The second technique is to replace the conventional SRAM memory in a TCAM with an array of programmable vias (or electrolyte non-volatile memory). Special programming circuitry is designed to read/write memory bits from/to the programmable via array because they do not simply store data in the form of low and high voltage levels. We also devised a new TCAM cell design to further reduce power consumption in TCAMs by taking full advantage of 3D-IC technology. A 1024 times 144-bit TCAM using the proposed schemes is implemented with 1.0-V 65 nm CMOS technology. Our analysis and simulations have shown that the proposed monolithically stacked 3D-TCAM can reduce the total dynamic power consumption by almost 3.5 times and increase TCAM cell density by about 4 times in comparison with a conventional 2D-TCAM chip of the same capacity.

Published in:

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Date of Conference:

18-21 May 2008

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