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Low-power short-channel single-ended current-steered CMOS logic-gate for mixed-signal systems

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2 Author(s)
Taparia, A. ; Dept of Electr. Eng., Univ. of Texas at Dallas, Richardson, TX ; Viswanathan, T.R.

Low-power CMOS logic circuits operated from a fixed supply voltage can result in uncontrolled conduction over process and temperature variation. Large current-pulses flowing during the logic transitions also cause power-supply noise. Current steered logic known as CSL can mitigate these problems. Here, a fixed bias-current is steered between two distinct paths during the transition between logic states. Constant supply-current eliminates switching noise on the power supply line. The current-biased circuit presented here operates like a normal CMOS gate preserving many of its desirable properties. The key modification is that the output static-voltage of the gate is used to steer the bias current between two paths. During the transition the bias current is used for pulling-up the output node. During the pull-down phase a small local capacitance is charged to provide the current pulse needed for pull-up. The current source resistance in conjunction with the local decoupling capacitor acts as a bypass for the impulse current needed for quick pull-up. This new circuit operates over a wide range of bias currents and, the corresponding speeds vary proportionately. These current-steered CMOS gates (CS- CMOS) are specially targeted for use in low-power, wide dynamic range mixed-signal applications where supply noise must be minimized. Circuit operation and simulation results are presented.

Published in:

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Date of Conference:

18-21 May 2008