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this paper a new ADC architecture of flash type is proposed. This proposed N-bit flash ADC replaces the (2N-1)-to- N encoder with two (2N/2 -1)-to-(N/2) encoders to accomplish the encoding of the least significant bits and the most significant bits respectively. A 6-bit ADC of this architecture is implemented. The physical circuit is more compact than the existing ones. Power, processing time and area cost are all minimized. In addition, a new encoding algorithm is proposed to enhance the bubble error tolerance of an ADC. The encoders that have the capability of removing the bubble errors always suffer the problem of long latency. It becomes a bottleneck in the design of high speed flash ADC nowadays. In the proposed 6-bit ADC, the trade-off between bubble tolerance and latency is optimized by applying the proposed encoding algorithm into the encoder circuit design. Delay of 3 gate-levels or fewer is required for processing the encoding and the maximum error induced bubble is 7 LSB. Simulation results demonstrate the benefits introduced above. This new flash ADC offers an excellent choice for modern high speed ADC application.
Date of Conference: 18-21 May 2008