We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Low-power static and dynamic high-voltage CMOS level-shifter circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Khorasani, M. ; Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB ; van den Berg, L. ; Marshall, P. ; Zargham, M.
more authors

Pseudo-NMOS level-shifters consume large static current making them unsuitable for portable devices implemented with HV CMOS. Dynamic level-shifters help reduce power consumption. To reduce on-current to a minimum (sub-nanoamp), modifications are proposed to existing pseudo-NMOS and dynamic level-shifter circuits. A low power three transistor static level-shifter design with a resistive load is also presented.

Published in:

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Date of Conference:

18-21 May 2008