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A new SRAM circuit technique based on dynamically adjusting the wordline voltage swing is proposed in this paper for reducing the leakage power consumption and enhancing the data stability in static memory banks. With the proposed technique, the wordline voltage swing is reduced in order to suppress the voltage disturbance at the data storage nodes during a read operation. The stability of a minimum sized standard six transistors (6T) SRAM cell is thereby significantly enhanced. Alternatively, during a write operation the wordline signal has a full voltage swing in order to achieve write-ability with a high write margin. With the proposed circuit technique, the static noise margin is enhanced by up to 122% as compared to the conventional full-voltage-swing 6T SRAM circuits with minimum sized transistors. Furthermore, the leakage power consumption with the proposed technique is reduced by 51% as compared to the conventional full-voltage-swing circuits sized for data stability in a 65nm CMOS technology.