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A clockless ultra low-noise low-power wireless implantable neural recording system

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2 Author(s)
Ming Yin ; Electr. & Comput. Eng. Dept., North Carolina State Univ., Raleigh, NC ; Ghovanloo, M.

Sharp digital transitions cause interference in low-noise mixed-mode IC designs. This issue is quite significant during clock transitions, which drive tens to thousands of gates depending on the complexity of the system. Many remedies have been proposed ranging from physical layout designs to shifting signal spectrum. However, nothing would probably be more effective than rooting the problem out by eliminating the clock itself. In this paper, we present a clockless ultra low-noise 4-channel wireless implantable neural recording system based on time division multiplexing (TDM) of pulse width modulated (PWM) signals with minimum substrate noise and interference. We have utilized a modified integrating ADC scheme to both sample and modulate the analog input channels while managing the switching times such that no switching occurs during sensitive sampling onsets. We have also reduced size and power consumption of the chip by the digitization circuitry to the receiver side. The chip has been implemented in the AMI 0.5-mum CMOS, occupying 0.81 mm2 and consuming 4.8 mW at +1.5 V when all channels are active. The measured input referred noise for the entire transmitter in 0.1 Hz~10 kHz range is only 7.3 muV.

Published in:

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Date of Conference:

18-21 May 2008