A low power 90-nm CMOS motion estimation processor implementing dynamic voltage and frequency scaling (DVFS) and fast motion estimation algorithm

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of tine advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorifna can adaptively predict tire optimum supply voltage (V
D
) and the opflinuin clock frequency (ƒ
c
) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter a nd DVFS controller, was reduced to 29.1 μW, which was only 3% that of a conventional ME processor.