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Parallelism to reduce power consumption on FPGA spatiotemporal image processing

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2 Author(s)
Atabany, W. ; Inst. of Biomed. Eng., Imperial Coll. London, London ; Degenaar, P.

Portable image processing systems require algorithms which reduce the power consumption while maintaining video rate operation. This paper describes how splitting the data stream into multiple processing pipelines can reduce power consumption in contrast to the traditional spatial (pipeline) parallel processing technique. Real-time image processing system functions (Sobel filters and anisotropic diffusion) were implemented to show the principle of the technique. Our results show that partitioning the image into multiple sections gives increasing benefits with shorter processing times, and up to 45% drop in the power consumption.

Published in:

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Date of Conference:

18-21 May 2008