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High-speed radio-frequency (RF) applications of 2D HR real-time spatio-temporal digital filters in smart antenna arrays require architectures that are capable of high throughputs. A novel systolic-array architecture is proposed for such filters that operate at a throughput of one-frame-per-clock-cycle (OFPCC). This architecture uses a 2D extension of a well-known ID look-ahead (LA) speed maximization technique to achieve low critical path delays. A method is proposed, simulated, implemented and tested for the broadband beamforming of temporally down-converted RF signals. Temporal down-conversion is used in direct-conversion receivers, implying potential wireless applications. The prototype is operational on a Xilinx 4vsx35ff668-10 FPGA device at a clock frequency of 100 MHz, thereby achieving the required real-time OFPCC frame rate of 100 Million frames/sec. Implementations using high-speed VLSI technologies are envisaged and will facilitate 2D IIR filtering at GHz frame-rates.