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A low-power-consumption 53-GHz (V-band) low-noise amplifier (LNA) using standard 0.13 mum CMOS technology is reported. To achieve sufficient gain, this LNA is composed of four cascaded common-source stages. Current-sharing technique is adopted in the third and the four stage to reduce the power dissipation. The output of each stage is loaded with an LC parallel resonance circuit to maximize the gain at the design frequency. This LNA achieved voltage gain (Av) of 14 dB, very low noise figure (NF) of 6.13 dB, input referred 1-dB compression point (P1 dB-in) of -20 dBm, and input third-order inter-modulation point (IIP3) of -9 dBm at 53 GHz. It consumed only a very small dc power of 10.56 mW. In addition, the chip area was only 0.91times0.58 mm2, including all the test pads and bypass capacitors.