By Topic

A low-power V-band CMOS low-noise amplifier using current-sharing technique

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hong-Yu Yang ; Dept. of Electr. Eng., Nat. Chi Nan Univ., Puli ; Yo-Sheng Lin ; Chi-Chen Chen ; Wong, S.S.

A low-power-consumption 53-GHz (V-band) low-noise amplifier (LNA) using standard 0.13 mum CMOS technology is reported. To achieve sufficient gain, this LNA is composed of four cascaded common-source stages. Current-sharing technique is adopted in the third and the four stage to reduce the power dissipation. The output of each stage is loaded with an LC parallel resonance circuit to maximize the gain at the design frequency. This LNA achieved voltage gain (Av) of 14 dB, very low noise figure (NF) of 6.13 dB, input referred 1-dB compression point (P1 dB-in) of -20 dBm, and input third-order inter-modulation point (IIP3) of -9 dBm at 53 GHz. It consumed only a very small dc power of 10.56 mW. In addition, the chip area was only 0.91times0.58 mm2, including all the test pads and bypass capacitors.

Published in:

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Date of Conference:

18-21 May 2008