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Scalable VLSI architecture for K-best lattice decoders

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2 Author(s)
Shabany, M. ; Edward S. Rogers Sr. Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON ; Gulak, P.G.

A scalable pipelined VLSI architecture for K-best lattice decoders featuring an efficient operation over infinite lattices is proposed. The proposed architecture operates at a significantly lower complexity than currently reported schemes. The key contribution is a means of expanding/visiting the intermediate nodes of the search tree on-demand, rather than exhaustively along with three types of distributed sorters operating in a pipelined structure. The combined expansion and sorting cores are able to find the K best candidates in just K clock cycles. Its support of the unbounded lattice decoding distinguishes our work from previous K-best strategies. Since the expansion and sorting cores cooperate on a data-driven basis, the architecture is well-suited for a pipelined parallel VLSI implementation. The proposed architecture has the lowest latency reported to-date, fixed critical path independent of the constellation order, on-demand expansion scheme, efficient distribute sorters, pipelined high-throughput implementation, and is scalable to higher number of antennas/constellation orders.

Published in:

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Date of Conference:

18-21 May 2008