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We present a ROM based logic design technique using reduced ROM size by eliminating identical rows and columns along with fast and low power single transistor cells. It substantially reduces the critical path length and thereby, improves the performance yet achieves low-power dissipation due to reduced number of switching. We present the ROM based design of a carry select adder (CSA) and two parallel prefix adders, which achieve more than 30% (in 32 bit adder) delay reduction over their conventional designs at 90 nm technology with as low as 9% (CSA) active power increase.
Date of Conference: 18-21 May 2008