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Switching activity reducing layered decoding algorithm for LDPC codes

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3 Author(s)
Shu-Cheng Chou ; Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei ; Mong-Kai Ku ; Chia-Yu Lin

A switching activity reducing decoding algorithm for low-density parity check (LDPC) codes is proposed. Our modified horizontal layered decoding algorithm reduces active node switching activities to lower LDPC decoder power consumption. Layered nodes are periodically refreshed to minimize coding gain degradation. A low hardware overhead partially parallel LDPC decoder architecture is also described. Simulation results show that our algorithm reduces the number of LDPC decoder operations up to 62.5% compared to the original layered decoding and improves the original vertical layered Lazy Scheduling much with little performance loss.

Published in:

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Date of Conference:

18-21 May 2008