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VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX

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5 Author(s)
Yeong-Luh Ueng ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu ; Chung-Jay Yang ; Zong-Cheng Wu ; Chen-Eng Wu
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In this paper, we modify a previously proposed decoding algorithm and propose a VLSI architecture to decode the quasi-cyclic low-density parity-check (QC-LDPC) code C used in the IEEE 802.16e standard. The modified decoding algorithm sequentially decodes a plurality of block codes for which its code length is much smaller than that of C. The proposed decoder can achieve a faster speed of convergence, lower decoding latency, higher throughput, and lower number of memory access as compared to the decoders using conventional turbo decoding message passing (TDMP) based on similar hardware complexity.

Published in:

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Date of Conference:

18-21 May 2008

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