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A 52mW 0.56mm2 1.2V 12b 120MS/s SHA-Free dual-channel Nyquist ADC based on mid-code calibration

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7 Author(s)
Hee-Cheol Choi ; Dept. of Electron. Eng., Sogang Univ., Seoul ; Young-Ju Kim ; Se-Won Lee ; Jae-Yeol Han
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This work describes a 12 b 120 MS/s dual-channel SHA-free Nyquist ADC based on a mid-code calibration technique eliminating offset mismatch between channels. The prototype ADC achieves a peak SNDR of 61.1 dB and a peak SFDR of 74.7 dB for input frequencies up to 60 MHz at 120 MS/s. Also, the measured DNL and INL are within plusmn0.30 LSB and plusmn0.95 LSB, respectively. The ADC fabricated in a 0.13 mum CMOS process occupies an active die area of 0.56 mm and consumes and consumes 51.6 mW.

Published in:

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Date of Conference:

18-21 May 2008

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