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This work describes a 12 b 120 MS/s dual-channel SHA-free Nyquist ADC based on a mid-code calibration technique eliminating offset mismatch between channels. The prototype ADC achieves a peak SNDR of 61.1 dB and a peak SFDR of 74.7 dB for input frequencies up to 60 MHz at 120 MS/s. Also, the measured DNL and INL are within plusmn0.30 LSB and plusmn0.95 LSB, respectively. The ADC fabricated in a 0.13 mum CMOS process occupies an active die area of 0.56 mm and consumes and consumes 51.6 mW.