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A power scalable 6-bit 1.2 GS/s flash Analog-to-Digital Converter (ADC) is designed in 90 nm CMOS. Rapid power on/off Track-and-Hold (T/H) and preamplifiers are proposed to provide scalable power consumption with sampling rate variation. Full transistor-level simulations of the ADC are presented from 1 MS/s (3 mW) to 1.2 GS/s (41 mW). At the maximum sampling rate the DNL is -0.9/+0.7 LSB and the INL is -0.8/+0.6 LSB. The ADC achieves 33 dB SNDR, 44 dB SFDR, and 0.9 pj/conversion-step at Nyquist from 1.2V power supply.