By Topic

A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
He-Gong Wei ; Analog and Mixed-Signal VLSI Laboratory, Faculty of Science and Technology, University of Macau, China ; U-Fat Chio ; Yan Zhu ; Sai-Weng Sin
more authors

A power scalable 6-bit 1.2 GS/s flash Analog-to-Digital Converter (ADC) is designed in 90 nm CMOS. Rapid power on/off Track-and-Hold (T/H) and preamplifiers are proposed to provide scalable power consumption with sampling rate variation. Full transistor-level simulations of the ADC are presented from 1 MS/s (3 mW) to 1.2 GS/s (41 mW). At the maximum sampling rate the DNL is -0.9/+0.7 LSB and the INL is -0.8/+0.6 LSB. The ADC achieves 33 dB SNDR, 44 dB SFDR, and 0.9 pj/conversion-step at Nyquist from 1.2V power supply.

Published in:

2008 IEEE International Symposium on Circuits and Systems

Date of Conference:

18-21 May 2008