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In this paper, the digital core of a low power RFID chip based on the EPC Gen 2 protocol is presented. EPC class 1 generation 2 is the most acceptable and comprehensive passive RFID protocol today. The novel dual mode architecture enables the chip to work in passive and battery-assisted modes controlled by reader. Several low power techniques are employed to reduce the power consumption of the chip which is essential in passive RFID tags. The chip has been designed and fabricated in standard 0.18um CMOS process. Power analysis shows that the digital core consumes 6.4 muW at IV supply voltage when it comcates wih the reader.