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New Non-Volatile Memory Structures for FPGA Architectures

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3 Author(s)
David Choi ; Electr. Eng. Dept., Univ. of California, Los Angeles, CA ; Kyu Choi ; John D. Villasenor

A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is described. The PEs have small area, can be combined with components that use low operational voltage on the same CMOS logic process, are non-volatile, enable the use of fast thin-oxide pass transistors, and are reprogrammable. A novel non-volatile flip-flop for use within the logical elements is presented as well. In combination, these methods enable programmable logic devices with improved area efficiency, the speed advantages of SRAM-based FPGAs, and a wide range of opportunities for power down strategies.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:16 ,  Issue: 7 )