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In this brief, a new approach is presented for parallel and pipelined implementation of repetitive multiple accumulations; and used that further to derive two modular structures for high-throughput realization. A set of N input operands (to be accumulated) are converted into a set of L operands of M=log2(N+1) -bit size by using L number of M-bit ripple counters in parallel on the input bit streams. In proposed structure-1, the outputs of the counters are added directly by a shift-add tree. In proposed structure-2, a new set of M number of L-bit operands are derived from the counter outputs, and shift-accumulated to derive the output sum. Both of the proposed structures are fully pipelined to process successive multiple accumulations without intermediate delay. It is shown further that both the structures can be used in multiple pipelined stages of successive accumulations, so that they could be conveniently scaled for implementation of multiple accumulation of large number of input words. The proposed structures are found to have much higher throughput and less area-delay complexity compared with serial-accumulator and pipelined adder based on carry-save addition as well.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:55 , Issue: 9 )
Date of Publication: Sept. 2008