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High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit

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3 Author(s)
Nagai, T. ; Res. Inst. of Electr. Commun., Tohoku Univ., Sendai ; Onizawa, N. ; Hanyu, T.

A high-speed timing verification scheme using delay tables is proposed for a large-scaled multiple-valued current- mode (MVCM) circuit. A multi-level input-signal transition in the MVCM circuit is decomposed of binary signal transitions whose behaviors are represented using delay tables as higher abstracted description than transistor-level one. This high-level abstraction makes it possible to greatly improve the timing-verification speed of the MVCM circuit. It is demonstrated that the timing-verification speed for a 32-digit radix-2 signed-digit adder in the proposed method is about 1000-times faster than that in a conventional HSPICE-based approach with maintaining high delay-estimation accuracy.

Published in:

Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on

Date of Conference:

22-24 May 2008

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