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Design of High-Performance Quaternary Adders Based on Output-Generator Sharing

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2 Author(s)
Hirokatsu Shirahama ; Res. Inst. of Electr. Commun., Tohoku Univ., Sendai ; Takahiro Hanyu

Simple implementations of quaternary full adders are proposed for a high-performance multi-processor which consists of many processing elements (PEs). Arbitrary quaternary functions are represented by the combination of input-value conversion and several quaternary output generations. The use of appropriate input-value conversion makes it possible to reduce the number of output generators, which improves the performance of the resulting quaternary full adders. For example, two kinds of single PEs including a quaternary full adder and two flip-flops are implemented using the proposed method and their efficiencies are demonstrated in terms of delay and power dissipation in comparison with those of a corresponding binary CMOS implementation.

Published in:

38th International Symposium on Multiple Valued Logic (ismvl 2008)

Date of Conference:

22-24 May 2008