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EDA to the Rescue of the Silicon Roadmap

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1 Author(s)
Williams, T.W. ; Synopsys, Inc., Mountain View, CA

Summary form only given. Since the invention of the transistor, new technology nodes have been added approximately every two years. This march of progress has yielded smaller transistors that run about 40% faster with each geometry scaling, fulfilling the promise and industry-defining mantra of "smaller, faster, cheaper!". Now, in the realm of 65- and 45-nanometer design and manufacturing, the industry is confronted by multiple complex and stubborn challenges: silicon technology keeps shrinking, but doesn't advance in speed at the same rate. The high-k dielectric announcements have yet to be proven manufacturable, and copper interconnect is already hitting the wall. We are driving to the edge of the silicon roadmap, but there is no viable alternative to CMOS within our reach. Not coincidentally, several companies are announcing their intention to stop internal R&D at the 45 nanometer node and use foundry-supplied processes at 32 nanometers and below. The electronics industry ecosystem is at a fork in the road: those few who can afford it will keep rushing to 45 nanometers and maybe beyond, to 32 and 25 nanometers; the rest will hold at 130 or perhaps 90 nanometers, trying to get the most out of those processes that they can. In both cases it is EDA that will come to the rescue. Advanced EDA provides a competitive advantage at 90 nanometers and above, and is a matter of plain survival at 65 nanometers and below. In 2006 only 10% of IC design starts have been at 90 nanometers and below (source: IBS), but they have generated more than 30% of silicon (source: VLSI Research), and absorbed more than 50% of all the engineering effort (source: SNUG '06). Without EDA, more EDA, or more advanced EDA, when design starts at 90 nanometers and below exceed 30% in 2 years (source: IBS), twice as many engineers will be needed. EDA innovation is the gear that enables design for low power, design for manufacturing and yield (which encompasses design for test), and design for v- ariability. The challenges faced by tools for multiple-valued logic clearly mirror those challenges faced by binary logic EDA tools. EDA is not only the enabler for quality in electronic design; it is truly "where electronics begins".

Published in:

Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on

Date of Conference:

22-24 May 2008