An RF amplifier implemented by wafer-scale three-dimensional integration of three completely fabricated silicon-on-insulator wafers is demonstrated. The MOSFETs are on the top and bottom tier with middle-tier matching circuits. Measured amplifier performance agrees well with simulation and the footprint is approximately 40% smaller than the conventional 2D layout.
Published in:
Electronics Letters
(Volume:44
,
Issue:
12
)
Date of Publication: June 5 2008