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Quad-level bit-stream adders and multipliers with efficient FPGA implementation

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3 Author(s)
Ng, C.W. ; Dept. of Electr. & Electron. Eng., Hong Kong Univ., Kowloon ; Wong, N. ; Ng, T.S.

Novel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (>76% hardware savings) and faster (>93% higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six- input look-up tables.

Published in:

Electronics Letters  (Volume:44 ,  Issue: 12 )

Date of Publication:

June 5 2008

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