By Topic

A Partial Scan Based Test Generation for Asynchronous Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Vasudevan, D.P. ; Sch. of Inf., Univ. of Edinburgh, Edinburgh ; Efthymiou, A.

Test Generation for asynchronous circuit is a hard problem mainly due to the absence of a global clock. Full scan design based test generation of asynchronous circuits seems to be feasible but at an expense of large area overhead. Partial scan should be a better option with lower area overhead but there is no known systematic way of selecting which asynchronous state-holding elements to scan. This paper presents a partial scan and automatic test generation methodology based on a novel adaptation of BALLAST for asynchronous circuits and time frame unrolling. Balanced structures are used to guide the selection of the state-holding elements that will be scanned. A cyclic to acyclic conversion of the input circuit is used to create a combinational circuit for which test patterns are easily generated using well known methods. These test patterns are then used to test the original circuit. Fault coverage and area overhead results of this method are obtained and analyzed with full scan and other methods.

Published in:

Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on

Date of Conference:

16-18 April 2008