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A triangular-modulated spread-spectrum clock generator using a Delta-Sigma-modulated fractional-N phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to implement the modulated fractional counter with increased Delta-Sigma operation speed. In addition, the phase mismatching error in the phase-interpolated PLL with multiphase clocks can be randomized, and finer frequency resolution is achievable. With a frequency modulation of 33 kHz, the measured peak power reduction is more than 11.4 dB under a deviation of plusmn0.37%. Without spread-spectrum clocking, the PLL generates 2.4-GHz output with 18.82-ps peak-to-peak jitter. After spread-spectrum operation, the measured up-spread and down-spread jitter can achieve 52.59 and 56.79 ps, respectively. The chip occupies 950 times 850 mum2 in 0.18-mum CMOS process and consumes 36 mW.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:56 , Issue: 1 )
Date of Publication: Jan. 2009