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A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing

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3 Author(s)
Kiyoto Ito ; Dept. of Frontier Inf., Univ. of Tokyo, Tokyo ; Benjamas Tongprasit ; Tadashi Shibata

In this paper, a computational digital pixel sensor (DPS) equipped with an on-chip image-processing capability has been developed. In order to resolve the interconnection bottleneck between the sensor array and on-chip processing units, a new block-readout architecture has been proposed and implemented on the chip. The data from the sensor array are read out in a form of a pixel block compatible to kernel image processing, and they are processed in parallel by on-chip processing units. Such an architecture has enabled us to carry out an efficient kernel processing using a linear array of single-instruction-multiple-data processing units. In order to demonstrate the advantage of such an architecture, a rank-order filtering circuit has been implemented on the chip as a case study of the on-chip image processing. In this paper, a binary-search rank-order filtering algorithm has been implemented in a simple circuitry. A proof-of-concept chip having an array of 64 times 48 pixels was designed and fabricated using a 0.35-mum CMOS technology, and the concept has been verified by the measuremet of fabricated chips.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:56 ,  Issue: 1 )