Skip to Main Content
We propose a method to implement NAND and NOR logical operations using nonlinear vertical-cavity semiconductor gates based on saturable absorption in semiconductor quantum wells. The device is designed to exhibit an inverse saturable absorber behavior, i.e., high throughput at low input energy and low throughput at high input energy level. The effects of different design parameters on the device performance are discussed. Numerical simulations are carried out to demonstrate dynamic operation of the device. The main advantages of the proposed implementation rest on key features of the semiconductor gate, such as passive and polarization-independent operation, and compactness.