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Hierarchical Instruction Register Organization

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5 Author(s)
Black-Schaffer, D. ; Comput. Syst. Lab., Stanford Univ., Stanford, CA ; Balfour, J. ; Dally, W.J. ; Parikh, V.
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This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient filter cache as a baseline and examines the benefits from 1) removing the tag overhead, 2) distributing the storage, 3) adding indirection, 4) adding efficient NOP generation, and 5) sharing instruction memory. The result is a hierarchical instruction register organization that provides a 56% energy and 40% area savings over an already efficient filter cache.

Published in:

Computer Architecture Letters  (Volume:7 ,  Issue: 2 )

Date of Publication:

July-Dec. 2008

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