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A new test data compression scheme is introduced in this paper. The proposed scheme encodes the test data provided by the core vendor, using a new and very effective compression scheme based on OLEL coding. In this scheme, codeword is divided into two parts according to the position: odd bits and even bits. The odd bits of codeword are used to represent the length of runs and the even bits of codeword are used to represent whether a run is finished. The length of codeword is in accordance with the distribution of the length of run in actual test data, and thus, significant compression improvements compared with the already known schemes are achieved. A simple architecture is proposed for decoding the compressed data on chip. Its hardware overhead is very low and comparable to that of the most efficient methods in the literature. Experimental results for the six largest ISCAS-89 benchmark circuits show that the proposed scheme is obviously better than the already known schemes in the aspects of compression ratio and the decompression structure, such as Golomb, FDR, and MTC coding schemes.