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Integrated ISS and FPGA SoC HW/SW Co-verification environment design

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4 Author(s)
Xunying Zhang ; Xian Microelectron. Technol. Inst., Xian ; Fei Hui ; Qiang Wang ; Xubang Shen

This paper developed an integrated ISS and FPGA SoC co-verification platform named MLCV, introduced the overall structure and principle of MLCV, and described each component's function of MLCV. Processor is modeled by an ISS that interface with the source-level debugger. The peripherals are implemented in the FPGA board. Communication between ISS and FPGA is encapsulated by a co- verification wrapper. To synchronize the bus operation, the on-chip bus protocol is implemented in FPGA. As a bus master, the ISS's peripheral access information is generated by the co-verification wrapper. SoC architecture supported by MLCV is limited by the on- chip bus protocol.

Published in:

Computer Supported Cooperative Work in Design, 2008. CSCWD 2008. 12th International Conference on

Date of Conference:

16-18 April 2008

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