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Millimeter-wave communication systems are now receiving significant interest. One of the applications of these systems is for short range communication delivering multi-gigabit per second performance. An important component in these high speed communication systems is the frequency synthesis where the internally generated high frequency voltage controlled oscillator (VCO) output is stabilized by comparing it to a low frequency and low phase noise external crystal. In order to compare and stabilize the output, frequency dividers are utilized in the phase locked loop. Current Mode Logic (CML) dividers provide reasonably large division bandwidth, which can match the VCO's wide-range output frequency. The design procedure of the CML frequency divider involves determining transistor sizes that ensure self-oscillation. However, this condition is sufficient but not necessary to design a divider. In this paper a new method to optimize the transistor sizes for CML frequency dividers is proposed which is shown to increase the maximum operating frequency and reduce the power dissipation. The proposed method is used to build a 2:1 static CML divider, fabricated on 0.13-mum CMOS, which achieves a division range from 12 to 40 GHz with power dissipation of 12 mW.