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Fault tolerant scheduling of precedence task graphs on heterogeneous platforms

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3 Author(s)
Anne Benoit ; ENS Lyon, Université de Lyon, LIP laboratory, UMR 5668, CNRS - INRIA - UCBL, France ; Mourad Hakem ; Yves Robert

Fault tolerance and latency are important requirements in several applications which are time critical in nature: such applications require guaranties in terms of latency, even when processors are subject to failures. In this paper, we propose a fault tolerant scheduling heuristic for mapping precedence task graphs on heterogeneous systems. Our approach is based on an active replication scheme, capable of supporting epsiv arbitrary fail-silent (fail-stop) processor failures, hence valid results will be provided even if epsiv processors fail. We focus on a bi-criteria approach, where we aim at minimizing the latency given a fixed number of failures supported in the system, or the other way round. Major achievements include a low complexity, and a drastic reduction of the number of additional communications induced by the replication mechanism. Experimental results demonstrate that our heuristics, despite their lower complexity, outperform their direct competitor, the FTBAR scheduling algorithm [3].

Published in:

Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on

Date of Conference:

14-18 April 2008