Skip to Main Content
Interrupt coalescing (IC) technique has been used in general-purpose operating systems to mitigate receive livelock (RL) problem in gigabit Ethernet network hosts. Schemes for dynamically tuning the interrupt coalescing behavior of a communication interface based on traffic load or system state have been proposed. However, all the existing IC schemes are designed using heuristics. In this paper we present an analytical model for the IC technique and carry out a detailed study of existing IC schemes in terms of their performance characteristics including system goodput, CPU consumption and latency. We validate our analysis through measurement-based experiments.