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Design of Highly-Parallel, 2.2Gbps Throughput Signal Detector for MIMO Systems

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4 Author(s)
Liang Liu ; State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai ; Xiaojing Ma ; Fan Ye ; Junyan Ren

This paper presents a field-programmable gate array (FPGA) implementation of a new multiple-input multiple-output (MIMO) signal detection algorithm applicable to ultra-high throughput MIMO communication systems. The algorithm simplifies the computation significantly compared to traditional K-Best algorithm, and with negligible bit error ratio (BER) degradation. A highly-parallel structure is implemented on the Xilinx Virtex-4 (XC4VLX200) platform, which achieves 2.2 Gbps detection throughput and is about four times over previous implementation. Moreover, a pre-processing method is realized to reduce the number of multipliers inside the detector and shrinks the critical path delay down to 6.79 ns. Together with candidate-sharing-architecture to further save the hardware cost, a high speed, compact signal detector for MIMO systems is demonstrated.

Published in:

Communications, 2008. ICC '08. IEEE International Conference on

Date of Conference:

19-23 May 2008