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Clock-skew errors in time-interleaved (TI) analog-to-digital converters (ADCs) importantly degrade the linearity of such converters. These nearly constant but unknown errors, which must not be confused with random jitter, prevent TI ADCs from performing uniform sampling. This paper proposes a mixed-signal clock-skew calibration technique and explores its limitations to perform a background calibration. Compared to the existing all-digital calibration techniques, ours distinguishes itself by the simplicity of its hardware elements. On the other hand, compared to the all-analog ones, ours keeps the inherent robustness of a digital clock-skew detection. A demonstrator shows the feasibility of our technique. This demonstrator consists of two 10-bit commercial ADCs, a field-programmable gate array to implement a digital clock-skew detector, and an application-specific integrated circuit in a CMOS 0.35-mum technology to implement a digitally trimmable multiphase sampling clock generator. In this highly hostile environment of interconnected discrete components, our demonstrator can correct an initial clock skew of thousands of picoseconds with a granularity of 1.8 ps.