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An 8-bit 600 megasamples-per-second (MSPS) analog-to-digital converter (ADC) has been implemented in 0.18-mum CMOS to achieve a minimum signal-to-noise-and-distortion ratio (SNDR) of 40 dB and a spurious-free dynamic range (SFDR) of 45 dB with input-signal bandwidth up to 200 MHz. The ADC is also capable of sampling up to 1 gigasamples/s and maintaining 39-dB SNDR at an input-signal frequency of 55 MHz. Distributed track-and-hold (DT&H) is employed at the ADC front end to relieve the linearity burden on individual T&H subunit. Complementary resistor and capacitor averaging networks are employed before and after DT&H switches separately in order to alleviate offset- and switching-induced errors, respectively. The fabricated ADC occupies 0.5 mm2 in chip area and consumes 207 mW from a 1.8-V supply.