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Performance Enhancement in Ultra-Scaled SONOS FinFlash by Inclusion of High-k Dielectric in the Gate Stack

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8 Author(s)
Jahan, C. ; CEA/LETI-Minatec, Grenoble ; Nowak, E. ; Perniola, L. ; Gely, M.
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This paper presents the technological process and electrical behaviour of SONOS FinFlash devices fabricated on silicon-on-insulator (SOI) substrates and including HfO2 in the inter poly dielectric (IPD). Using trimming techniques, ultra-scaled devices were processed with aggressive dimensions down to 10 nm channel width and 30 nm gate length. Good performances are obtained in Fowler-Nordheim (FN) operation on these structures.

Published in:

Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 International Conference on Memory Technology and Design. NVSMW/ICMTD 2008. Joint

Date of Conference:

18-22 May 2008