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A power reduction technique is proposed for SRAM macros in which dual power supply scheme is combined with dynamic voltage scaling scheme. The test chip with 1Mb SRAM macro fabricated using 65nm CMOS process has demonstrated that the active power in low power mode is reduced by 25% compared to that of the conventional scheme. The leakage current at sleep mode is also decreased by three orders of magnitude compared to that of the conventional one.
Date of Conference: 18-22 May 2008