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A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems

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4 Author(s)
Jongsun Kim ; Sch. of Electron. & Electr. Eng., Hongik Univ., Seoul ; Bo-Cheng Lai ; Chang, M.-C.F. ; Verbauwhede, I.

This paper presents how a multi-core system can benefit from the use of a latency-aware memory bus capable of dual-concurrent data transfers on a single wire line: Source synchronous CDMA interconnect (SSCDMA-I) has been adopted to implement the memory bus of a shared-memory multi-core system. Two types of bus-based homogeneous and heterogeneous multi-core systems are modeled and simulated by a cycle-accurate simulation platform. Unlike the conventional time-division multiplexing (TDM) bus-based multi-core system that shows degradation in performance as the number of processing cores increases, the proposed SSCDMA bus-based multi-core shows higher performance up to 23.1% for 4 cores. The maximum latency of a heterogeneous multi-core system with a mix of traffic loads has been reduced up to 78%. These results demonstrate that the performance of multi-core systems can be improved with less cost and network complexity by reducing the bus contention interferences and by supporting higher concurrency in memory accesses that brings shorter critical word access latency.

Published in:

Computers, IEEE Transactions on  (Volume:57 ,  Issue: 12 )

Date of Publication:

Dec. 2008

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