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A 40-Gb/s Transimpedance Amplifier in 0.18- \mu m CMOS Technology

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2 Author(s)
Jun-De Jin ; Dept. of Electr. Eng. & Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu ; Shawn S. H. Hsu

A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology. From the measured S-parameters, a transimpedance gain of 51 dBOmega and a 3-dB bandwidth up to 30.5 GHz were observed. A bandwidth enhancement technique, pi-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 X 0.46 mm2. The proposed CMOS TIA presents a gain-bandwidth product per DC power figure of merit (GBP/Pde) of 180.1 GHzOmega/mW.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:43 ,  Issue: 6 )