By Topic

Bit-serial arithmetic: A novel approach to fuzzy hardware implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Dick, S. ; Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB ; Gaudet, V. ; Huiqing Bai

We propose a novel method of implementing fuzzy logic operations in digital hardware using bit-serial arithmetic. In this approach, signals in a fuzzy system are represented as bit-serial vectors, and manipulated using bit-serial techniques. The advantages of the bit-serial representation are a very simple implementation of min and max operations, and the ability to control the precision of a computation in time, rather than in silicon area. We present a prototype architecture for a fuzzy controller utilizing bit-serial computations, which is implemented in an FPGA. On a Altera Stratix II EP1S80B956C6 FPGA we achieve a throughput of 5.265 million inferences per second, at a clock rate of 94.77 MHz. LUT utilization is approximately 1% of the FPGA device.

Published in:

Fuzzy Information Processing Society, 2008. NAFIPS 2008. Annual Meeting of the North American

Date of Conference:

19-22 May 2008