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Multiuser/multiple-input-multiple-output detectors that use Markov chain Monte Carlo (MCMC) simulation techniques to obtain likelihood of information bits have been developed recently. In this paper, we explore the implementation details of one such detector and present an efficient hardware architecture of it. The first step in development of this architecture is to derive a log-domain version of the Gibbs sampler, an efficient method of obtaining samples of MCMC simulator. This formulation is numerically stable and can operate with low precision. The log- domain formulation also lends itself to a hardware architecture that involves only addition, subtraction, and compare operations. Moreover, pipelining is introduced in the proposed architecture straightforwardly. We also explore the word-length requirement of the developed architecture through computer simulations.