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Realization of Silicon-Germanium-Tin (SiGeSn) Source/Drain Stressors by Sn implant and Solid Phase Epitaxy for strain engineering in SiGe channel P-MOSFETs

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9 Author(s)
Grace Huiqi Wang ; Silicon Nano Device Laboratory (SNDL), Dept. of Electrical and Computer Engineering, National University of Singapore (NUS), Singapore 117576. ; Eng-Huat Toh ; Taw Kuei Chan ; Thomas Osipowicz
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We report the first demonstration of silicon-germanium-tin (SiGeSn) source and drain (S/D) stressors formed by Sn implant and solid-phase epitaxy (SPE). SPE was developed to achieve high levels of Sn substitutionality in SiGe S/D, to induce compressive strain in the channel. No recess etch or epi deposition steps were required, leading to minimal incremental process cost. SiGeSn S/D can be easily integrated in a standard CMOS process. Sub-50 nm p- FETs were fabricated. With a substitutional Sn concentration of 6.6% in SiGe S/D, having an equivalent lattice constant to that of Si0.4Ge0.6, enhancement of IDsat and hole mobility (muhole) are 48% and 88% respectively, over p-FETs without Sn implant. With the demonstration of SiGeSn S/D stressors, we provide a technology extension to SiGe S/D technology for further p-FET enhancement.

Published in:

VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on

Date of Conference:

21-23 April 2008