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Access Transistor Design and Optimization for 65/45nm High Performance SOI eDRAM

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8 Author(s)
G. Wang ; IBM Semiconductor Research & Development Center, 2070 Route 52, Hopewell Junction, NY 12533. Phone: +1-845-892-9034, Fax: +1-845-892-6576, Email: ; P. Parries ; K. Cheng ; K. Amarnath
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A 65 nm prototype embedded DRAM macro on partially depleted SOI (PD-SOI) substrate capable of <2. 0ns latency and the enabling cell technology have been described previously [1,2]. In this paper, we focus on the cell design and optimization for best retention and performance which have been extended to the 45 nm node.

Published in:

VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on

Date of Conference:

21-23 April 2008