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A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory

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10 Author(s)
Hsin-Heng Wang ; Powerchip Semicond. Corp., Hsinchu ; Chiu-Tsung Huang ; Shin-Hsien Chen ; Kuo, R.
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In this paper, we present our study of a method to improve nonuniform erasing speeds caused by slow edge cells (cell 0 and cell 31). Simulation and measurement results showed that the slow erasing speed at edge cells is resulted from the coupling effect of select gate (SG) transistors. Moreover, several extra bias voltages were forced on the pass wordlines to evaluate the electrostatic potential difference and to improve erase uniformity. Simulation result and measurement data demonstrated that 0.4 V of the extra bias voltage can improve the uniformity of the erasing speed in nano-scale NAND flash memory.

Published in:

VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on

Date of Conference:

21-23 April 2008